ADC for low-energy radios

Imec and Holst Centre have developed an ultralow-power 8-bit analog to digital convertor consuming 30 fJ of energy per conversion step. It is especially suitable for upcoming low-energy radios in the ISM bands such as low-energy Bluetooth or IEEE 802.15.6 for body-area networks.

By carrying out all the charge redistribution passively, the power consumption of the SAR ADC is already reduced compared with conventional SAR ADCs. An asynchronous controller is implemented to further minimise the power consumption and to allow operation on a single external sampling clock. The asynchronous implementation thus has no clock-driven precharge phase but instead self-synchronises the various building blocks to maximise the speed of operation and minimise the power consumption.

The chip was implemented in a 90 nm digital CMOS technology. Measurements on silicon show a power consumption of 69 µW at a sampling rate of 10 MS/s and a standby power of 17 nW. Since none of the ADC building blocks consumes any static power, the power consumption of the ADC scales linearly with the sampling frequency. The figure of 30 fJ/conversion step is maintained from 10 kS/s to 10 MS/s.